Memory Model C++11 – C++23About Me: alex.dathskovsky@speedata.io www.linkedin.com/in/alexdathskovsky https://www.cppnext.comAlex Dathskovsky | alex.dathskovsky@speedata.io | www.linkedin.com/in/a hazards • an instruction can be executed when its operands have been calculated or loaded from memory • an instruction stalls if operands are not availableAlex Dathskovsky | alex.dathskovsky@speedata com/in/alexdathskovsky Reordering Types • Data dependencies must be honored • C++ compiler may reorder any memory access under the as-if rule • Different processors have different reordering guarantiesAlex

rights reserved. Presenter: Haichen Shen, Yao Wang Amazon SageMaker Neo, Deep Engine Science Dynamic Model in TVM AWS AI© 2019, Amazon Web Services, Inc. or its Affiliates. All rights reserved. Models with models© 2019, Amazon Web Services, Inc. or its Affiliates. All rights reserved. Support dynamic model in TVM ● Support Any-dim in typing ● Use shape function to compute the type at runtime ● Virtual input_name = "data" input_shape = [tvm.relay.Any(), 3, 224, 224] dtype = "float32" block = get_model('resnet50_v1', pretrained=True) mod, params = relay.frontend.from_mxnet(block, shape={input_name:

Perspective Security Beyond Memory Safety Using Modern C++ to Avoid Vulnerabilities by DesignMax Hoffmann Security Beyond Memory Safety CppCon 2024 2 Security Beyond Memory Safety Using Modern C++ to Security Beyond Memory Safety CppCon 2024 3 FIFTY SHADES OF SHOOTING YOURSELF IN THE FOOT WITH A RAILGUNMax Hoffmann Security Beyond Memory Safety CppCon 2024 4Max Hoffmann Security Beyond Memory Safety CppCon Security Beyond Memory Safety CppCon 2024 6Max Hoffmann Security Beyond Memory Safety CppCon 2024 7Max Hoffmann Security Beyond Memory Safety CppCon 2024 8Max Hoffmann Security Beyond Memory Safety CppCon

A Relaxed Guide to memory_order_relaxed Hans Boehm Paul E. McKenney Google Facebook CPPCON 2020std::atomic/std::atomic_ref and memory_order_relaxed ● C++ atomic sacrificing the simple threads-as-interleaving semantics ● by passing memory_order enum values to explicit atomic operations. ● In particular, memory_order_relaxed allows arbitrary visibility reordering with respect About memory_order_relaxed? ● Just a load, just a store: Full control, excellent efficiency and scalability! ○ Assuming aligned machine-sized atomic objects, that is…What is Not to Like About memory_order_relaxed

© 2019 Apex.AI, Inc. Safe and certified software for autonomous mobility TM Practical memory pool based allocators for Modern C++ by Misha Shalem misha.shalem@apex.ai © 2020 Apex.AI, Inc.● CppCon Andreas Pasternak ● Quote: “Memory pools and allocators are only one piece of the solution” Today we going to talk about this one piece in (more) depth © 2020 Apex.AI, Inc.Memory allocations in real-time practically for C++ memory allocations? We asked an independent 3rd party safety assessor and the answer was “It should comply to Autosar C++ 14 Coding Guidelines regarding memory allocations” © 2020

Bar std::string Bar std::string Bar std::stringObject Introspection (OI) Goals • Byte level memory footprint analysis for objects • Complete object type hierarchies • Dynamic allocations and containers hierarchy from a given root type • Understand the layout in memory of the entire hierarchy • Understand how to interpret data at memory offsets • Understand containers • Compiler generated debug Object Introspection Measurement Code Code GenerationApplied Example 1 • Unused container memory: Unused Sz = (C.capacity() - C.size()) * sizeof(element) Name TypeName Number ElemStatSz Length

Systems - NUMA regions: - 4+ GPUs - 2+ CPUs - Systems becoming more hierarchical: even more memory domains - Software needed to reduce complexity CPU NIC GPU Tile 1 Tile 0 GPU Tile 1 Tile 0 Random access: access any element at random in constant time - Contiguous: a contiguous block of memory begin end begin end Contiguous Range begin end Range Random Access Range begin + 4Distributed to remote memory Node 0 Node 1 Write 12 -> 0x8f Communication Mechanisms- Message Passing - processes issue matching send and receive calls - RDMA - directly read/write to remote memory Node 0

Chair of WG21 SG14 Games Dev/Low Latency/Financial Trading/Embedded ● Editor: C++ SG5 Transactional Memory Technical Specification ● Editor: C++ SG1 Concurrency Technical Specification ● MISRA C++ and 1. SYCL, oneAPI, and ecosystem 2. SYCL 2020 features • Moving with the Times and Any Backend • Memory Spaces and Dimensions • Reductions and Group Algorithms 3. SYCL futures 9© The Khronos® Group Embedded Systems through Desktops to Supercomputers 12SYCL 2020 Major Features • Unified Shared Memory (USM) • Code with pointers can work naturally without buffers or accessors • Simplifies porting

eliminated” –Bjarne Stroustrup The Design and Evolution of C++Why do we need casts? 1. Work with raw memory 2. Navigate inheritance hierarchy C++ is a statically typed language Casts allow us to...Why do has_leaves = true;}; struct car {int model_year = 1982; }; void prune(tree* t) { t->has_leaves = false; } void drive(const car* c ) { printf("Driving %d\r\n", c->model_year); } int main() { const tree to float f = mustang.model_year; //implicit conversion from int to float drive((car*)&f); // driving a float return 0; }struct tree { bool has_leaves = true;}; struct car {int model_year = 1982; }; void

in-process interoperability.Run down of some approaches Just be like C? – post-1972 Common Object Model (COM) – 1993 Foreign function interface (libffi) – 1996 Simplified Wrapper and Interface Generator Windows, sizeof(wchar_t) == 2 • Non-Windows, sizeof(wchar_t) == 4 std::basic_string has memory implications. More on that later.What assumptions are being made? void get_size(size_t dev, long* returns the struct in registers, but the get_data_from() member function returns in caller provided memory. This is often unexpected but occurs using the MSVC compiler for x86 with stdcall (callee cleanup)