Comprehensive Rust(Español) 202412inicialización. .section .init.entry, "ax" .global entry entry: /* * Load and apply the memory management configuration, ready to enable MMU and * caches. */ adrp x30, idmap msr ttbr0_el1, x30 mov_i x30 set .L_TCR_TG1_4KB, 0x2 << 30 /* Disable translation table walk for TTBR1_EL1, generating a translation fault instead. */ .set .L_TCR_EPD1, 0x1 << 23 /* Translation table walks for TTBR0_EL1 are inner sharable L_TCR_SH_INNER, 0x3 << 12 /* * Translation table walks for TTBR0_EL1 are outer write-back read-allocate write-allocate 315 * cacheable. */ .set .L_TCR_RGN_OWB, 0x1 << 10 /* * Translation table walks for TTBR0_EL10 码力 | 389 页 | 1.04 MB | 10 月前3- Guía Práctica de RISC-V:
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